An exemplary method of forming trenched isolation structures is described with reference to FIGS. 1-3. Referring initially to FIG. 1, a semiconductor wafer 10 is illustrated in top view. Wafer 10 comprises a substrate 11. Substrate 11 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with a background p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Wafer 10 is shown to comprise a central (or center) region 12 and an edge region 14 surrounding the central region. Regions 12 and 14 are shown separated by a boundary 15 in the form of a dashed line.
It is to be understood that regions 12 and 14 are defined herein for purposes of explaining an invention which follows. There generally is not a clearly defined boundary between the central region 12 and edge region 14, but rather there is a transition between processing associated with region 12 and that associated with region 14. Regions 12 and 14 can thus be considered to correspond to areas of a wafer in which processing differences occur during fabrication of structures associated with the wafer. For instance, various fabrication processes are found to proceed at a different rate in the central region of a wafer than at the edge region, and the term “center-to-edge uniformity” is frequently utilized in quantitating a difficulty in maintaining constant processing conditions across an entire expanse of a semiconductor wafer surface. Regions 12 and 14 can be considered to correspond to regions across the wafer surface which experience different rates of semiconductor processing due to a lack of center-to-edge uniformity. The different rates can be associated with, for example, different rates of deposition and/or different rates of etching (sputtering), and can result from a lack of center-to-edge process uniformity during processing of wafer 10.
Wafer 10 is illustrated as comprising an upper surface 16, and a plurality of openings 18 (only some of which are labeled) are shown extending into such upper surface. Openings 18 are drawn at a scale far out of proportion to the typical size of openings 18 relative to wafer 10 in order to simplify the illustration. Wafer 10 will have a maximum dimension (such as, for example, a diameter of the shown circular-shaped wafer 10) on the order of several inches (such as, for example, 6 inches, 8 inches, 12 inches, etc.); and openings 18 will typically have a maximum dimension of from about 1 to 100 microns.
Openings 18 can be formed in various shapes, including, for example, circular shapes, oval shapes, rectangular (or trenched) shapes, etc, and are shown comprising rectangular shapes. In particular applications, openings 18 can correspond to trenches which are ultimately to be utilized for forming trenched isolation structures. Exemplary trenched isolation structures are shallow trench isolation structures, with the term “shallow” referring to a trench having a depth of less than about 1 micron.
FIG. 2 illustrates a cross section along the line 2—2 of FIG. 1, and illustrates a center-to-edge variation that can occur within openings 18. Specifically, the openings 18 formed within edge region 14 are deeper than the openings 18 formed within center region 12. Typical processing for forming openings within substrate 11 of wafer 10 utilizes photolithographic processing. A masking layer is formed and patterned across a surface of substrate 11, and subsequently the pattern of the masking layer is etched into the substrate with an appropriate etch chemistry. The masking layer is subsequently removed to leave the structure shown in FIGS. 1 and 2. Frequently, the etch chemistry will proceed more rapidly at the edge region of a wafer than at the central region, and accordingly the openings formed at edge region 14 are deeper than the openings formed in central region 12. A difference in depth between the shallowest openings in region 12 and the deepest openings in region 14 can be from about 100 Å to about 500 Å. Such difference in depth can cause problems in further processing.
FIG. 3 illustrates a layer 20 of insulative material formed over substrate 11 and within openings 18. The Insulative material of layer 20 can comprise, for example, silicon dioxide, and can be formed utilizing high density plasma chemical vapor deposition (HDP-CVD). Ultimately, the openings 18 filled with insulative material of layer 20 can be utilized as trenched isolation regions between integrated circuit devices (not shown). Accordingly, it can be desired that openings 18 be uniformly filled with insulative material of layer 20.
A problem resulting from the increased depth of the openings in edge region 14, relative to the openings in central region 12, is that the processing parameters suitable for filling the openings within the central region are not suitable for uniformly filling the openings within the edge region. Accordingly, keyholes (or voids) 22 can form within the openings 18 in edge region 14, with such keyholes corresponding to gaps within the insulative material formed within the openings. Keyholes 22 can alter the dielectric properties of the isolation regions comprising the keyholes, relative to the desired properties, and can detrimentally affect, or even destroy, suitability of the trenched regions for electrical isolation of adjacent circuit devices.
It is desirable to develop new methods for forming materials within openings across a semiconductor wafer substrate which overcome the prior art problems discussed with reference to FIG. 3.
The layer 20 shown in FIG. 3 can be deposited with various forms of equipment. Two exemplary apparatuses which can be utilized for depositing layer 20 are described with reference to FIGS. 4 and 5.
Referring to FIG. 4, a reaction chamber of a type available from Applied Materials as the ULTIMA HDP-CVD CHAMBER™ is shown diagrammatically as an apparatus 50. Apparatus 50 comprises a reaction chamber 52 surrounded by a sidewall 53. A first set of power coils 54 (typically RF coils) extends across a top of the reaction chamber, and another set of power coils 56 extends along the side of the reaction chamber.
Inlet ports 60 and 62 extend into sides of the reaction chamber, and an inlet port 64 extends through a top of the reaction chamber. Ports 60, 62 and 64 are utilized for introducing precursor (illustrated by arrows 65) into the reaction chamber.
An outlet 66 extends from a bottom of the reaction chamber. A valve 68 extends across the outlet. A pump 70 is provided in fluid communication with the outlet to withdraw materials (typically gaseous materials) from within the chamber and evacuate such materials as exhaust (indicated by an arrow 67).
A wafer holder 72 is provided within chamber 52, and a wafer 10 is shown supported by wafer holder 72. In operation, suitable precursors are flowed through ports 60, 62 and 64 to deposit a desired layer 20 (not shown in FIG. 4) across a surface of wafer 10. A plasma (not shown) is powered by coils 54 and 56 and utilized to enhance the deposition of material from precursors 65.
Referring to FIG. 5, an apparatus 80 corresponding to a Novellus™ system is illustrated schematically. Apparatus 80 comprises a reaction chamber 82 having a sidewall 83. Sidewall 83 includes a dome-shaped upper portion. Power coils 84 are provided around the dome.
Inlet ports 86 and 88 extend into chamber 82 and are utilized for introducing precursors (illustrated by arrows 89) into the reaction chamber. An outlet port 90 extends out of chamber 82, and is utilized for evacuating exhaust materials (illustrated by arrow 91) out of chamber 82. Exhaust port 90 can have a valve (not shown) extending therein, and can be in fluid communication with a suitable pump, such as, for example, a turbo pump (not shown).
A wafer holder 92 is provided within chamber 82, and a wafer 10 is shown supported by wafer holder 92. In operation, precursors 89 are flowed into chamber 82 and a plasma (not shown) is maintained with power coils 84 during deposition of a desired material of layer 20 (shown in FIG. 3, but not in FIG. 5) across an upper surface of wafer 10. The plasma creates reactive deposition precursors as well as providing ionic species which can be accelerated to the wafer via an RF bias applied to the wafer. Accordingly, sputtering (or etching) occurs simultaneously with deposition.